1. Field of the Invention
The present invention relates to planarization processes used during integrated circuit manufacturing; and more particularly to an improved spin-on-glass process in which the environment is controlled during the spread/flow-in step and other steps of the process.
2. Description of Related Art
Spin-on-glass (SOG) has been widely used in integrated circuit manufacturing to improve wafer surface planarity. A high degree of planarity on the wafer surface is needed for fine photolithographic resolution. Also, planarity is needed to avoid metal stringers after etching of the metal lines which might be left in impressions on the surface of the wafer and cause shorts on the device. Many articles have been published, for instance, in the annual VLSI Multilevel Interconnection Conferences, such as Ting, et al., "Planarization Process Using Spin-On-Glass", Proceedings Fourth International IEEE VLSI Multilevel Interconnection Conference, Jun. 15-16, 1987, pages 61-67. Also, background concerning the SOG coating principles can be found in Yonkoski, et al., "A Mathematical Model for Planarization of Microelectronic Topographies", Journal of the Electrochemical Society, Vol 141, No. 2, 1994, pages 585-593; and Sukanek, "A Model for Spin Coating with Topography", Journal of the Electrochemical Society, Vol. 136, No. 10, 1989, pages 3019-3026.
Many factors affect the results of a SOG coating profile. Properties of the materials used, including the surface tension, viscosity, solvent evaporation rate, and shrinkage due to high temperature curing are key factors in the ability of the SOG process to fill gaps and establish a planar surface. However, spin speed, SOG settling time, acceleration, the manner of dispensing the SOG, and the ambient during the coating process are important factors for establishing a quality coat on the device. There are many interacting factors involved in the SOG coating process including surface tension, SOG bulk viscosity, centrifugal force, and gravitational forces that the SOG experiences.
A conventional SOG coating process typically consists of the following steps:
1) Dispense SOG at a low wafer spin speed (e.g. 0-200 RPM).
2) Spread SOG at a medium spin speed to get uniform wafer coverage (e.g. 500-1000 RPM).
3) Flow-in (planarize) SOG at a slow speed (e.g. 500-1000 RPM).
4) Spin off the excess top layer SOG at a high speed (e.g. 2000-3000 RPM).
5) Transfer the wafer from the coater to a hot plate.
6) Bake/dry the SOG at higher temperatures.
There are several limitations to the conventional SOG coating process. First, there is a lower limit as to how slow the wafer may be spinned during the spread step, and a maximum amount of time during which the flow in step may be allowed to occur to avoid rapid viscosity changes due to loss of solvent. Further, the spin off rotation speed during the fourth step needs to be high enough to minimize excess SOG thickness on the top of wide metal structures. However, the spin off rotation speed cannot be too high such that unhardened SOG escapes filled in gaps in the underlying structure, leaving a void behind.
Further background concerning SOG coating process can be seen in U.S. Pat. No. 4,721,548 by Morimoto (SOG with etch back for semiconductor planarization); U.S. Pat. No. 4,775,550 by Chu, et al. (SOG with etch back for intermetal dielectric); U.S. Pat. No. 4,885,262 by Ting, et al. (chemically modified SOG); U.S. Pat. No. 5,003,062 by Yen (planarization process); U.S. Pat. No. 5,106,787 by Yen (high vacuum curing for SOG planarization).
Accordingly, it is desirable to provide a spin-on-glass process resulting in better filling of voids, better planarity, and thinner structures over wide metal features on the device.